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===Key features=== | ===Key features=== | ||
| − | * ''Multiple interchangeable CPU models.'' gem5 provides four | + | * ''Multiple interchangeable CPU models.'' gem5 provides four interpretation-based CPU models: a simple one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order CPU. These CPU models use a common high-level ISA description. In addition, gem5 features a KVM-based CPU that uses virtualisation to accelerate simulation. |
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| + | * ''[[GPU_Models|A fully integrated GPU]]'' model that executes real machine ISA and supports shared virtual memory with the host CPU. | ||
* ''[[Media:2015_ws_04_ISCA_2015_NoMali.pdf|A NoMali GPU model.]] '' gem5 comes with an integrated NoMali GPU model that is compatible with the Linux and Android GPU driver stack, and thus removes the need for software rendering. The NoMali GPU does not produce any output, but ensures that CPU-centric experiments produce representative results. | * ''[[Media:2015_ws_04_ISCA_2015_NoMali.pdf|A NoMali GPU model.]] '' gem5 comes with an integrated NoMali GPU model that is compatible with the Linux and Android GPU driver stack, and thus removes the need for software rendering. The NoMali GPU does not produce any output, but ensures that CPU-centric experiments produce representative results. | ||
| − | * ''[[Media:2015_ws_02_hansson_gem5_workshop_2015.pdf|Event-driven memory system.]]'' gem5 features a detailed, event-driven memory system including caches, crossbars, snoop filters, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4, DDR3/4, | + | * ''[[Media:2015_ws_02_hansson_gem5_workshop_2015.pdf|Event-driven memory system.]]'' gem5 features a detailed, event-driven memory system including caches, crossbars, snoop filters, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4/5, DDR3/4, GDDR5, HBM1/2/3, HMC, WideIO1/2. The components can be arranged flexibly, e.g., to model complex multi-level non-uniform cache hierarchies with heterogeneous memories. |
| + | |||
| + | * ''[[TraceCPU|A trace-based CPU]]'' model that plays back elastic traces, which are dependency and timing annotated traces generated by a probe attached to the out-of-order CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed CPU model. | ||
| − | * ''Homogeneous and heterogeneous multi-core.'' The CPU models and caches can be combined in arbitrary | + | * ''Homogeneous and heterogeneous multi-core.'' The CPU models and caches can be combined in arbitrary topologies, creating homogeneous, and heterogeneous multi-core systems. A MOESI snooping cache coherence protocol keeps the caches coherent. |
| − | * ''Multiple ISA support.'' gem5 decouples ISA semantics from its | + | * ''Multiple ISA support.'' gem5 decouples ISA semantics from its CPU models, enabling effective support of multiple ISAs. Currently gem5 supports the Alpha, ARM, SPARC, MIPS, POWER, RISC-V and x86 ISAs. See [[Supported Architectures]] for more information. |
* ''Full-system capability.'' | * ''Full-system capability.'' | ||
** '''Alpha''': gem5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability. | ** '''Alpha''': gem5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability. | ||
| − | ** '''ARM''': gem5 can model up to | + | ** '''ARM''': gem5 can model up to 64 (heterogeneous) cores of a Realview ARM platform, and boot [[ARM_Linux_Kernel|unmodified Linux]] and [[Android_Marshmallow|Android]] with a combination of in-order and out-of-order CPUs. The ARM implementation supports 32 or 64-bit kernels and applications. |
** '''SPARC''': The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver). | ** '''SPARC''': The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver). | ||
** '''x86''': The gem5 simulator supports a standard PC platform | ** '''x86''': The gem5 simulator supports a standard PC platform | ||
| − | * ''Multi-system capability.'' | + | * ''Multi-system capability.'' Multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks. |
* ''Power and energy modeling.'' gem5’s objects are arranged in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See [[Running_gem5#Experimenting_with_DVFS|how to run your own DVFS experiments]]. | * ''Power and energy modeling.'' gem5’s objects are arranged in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See [[Running_gem5#Experimenting_with_DVFS|how to run your own DVFS experiments]]. | ||
| − | * ''Co-simulation with SystemC.'' gem5 can be included in a SystemC simulation, effectively running as a thread inside the SystemC event kernel, and keeping the events and timelines synchronized between the two worlds. This functionality enables the gem5 components to interoperate with a wide range of System on Chip (SoC) component models, such as interconnects, devices and accelerators. | + | * ''[[Media:2015_ws_09_2015-06-14_Gem5_ISCA.pptx|Co-simulation with SystemC.]]'' gem5 can be included in a SystemC simulation, effectively running as a thread inside the SystemC event kernel, and keeping the events and timelines synchronized between the two worlds. This functionality enables the gem5 components to interoperate with a wide range of System on Chip (SoC) component models, such as interconnects, devices and accelerators. A wrapper for SystemC Transaction Level Modelling (TLM) is provided. |
=== Download === | === Download === | ||
| − | * The | + | * The canonical version of gem5 is available at https://gem5.googlesource.com/. (See the [[Repository]] page for details.) Auxiliary files are available on on our [[Download]] page. |
===Additional details=== | ===Additional details=== | ||
| − | * ''Application-only support.'' In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with | + | * ''Application-only support.'' In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with Linux emulation. |
| − | * ''Platforms.'' The gem5 simulator runs on most operating systems (Linux, MacOS X | + | * ''Platforms.'' The gem5 simulator runs on most operating systems (Linux, MacOS X, OpenBSD) and architectures (x86, x86-64, ARM, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC and/or clang. |
* ''Licensing.'' The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources. | * ''Licensing.'' The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources. | ||
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A list of [[publications]] using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5. | A list of [[publications]] using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5. | ||
| − | If you use gem5 in your research, we would appreciate a citation to, [http://dx.doi.org/10.1145/2024716.2024718 ''The gem5 Simulator,''] from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce. | + | If you use gem5 in your research, we would appreciate a citation to, [http://dx.doi.org/10.1145/2024716.2024718 ''The gem5 Simulator,''] from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce. In addition, please [[Publications|cite the specific features of gem5]] that you are using as part of your research. |
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===Acknowledgments=== | ===Acknowledgments=== | ||
The gem5 simulator has been developed with generous support from | The gem5 simulator has been developed with generous support from | ||
Latest revision as of 19:36, 29 August 2018
|
About
- The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.
Key features
- Multiple interchangeable CPU models. gem5 provides four interpretation-based CPU models: a simple one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order CPU. These CPU models use a common high-level ISA description. In addition, gem5 features a KVM-based CPU that uses virtualisation to accelerate simulation.
- A fully integrated GPU model that executes real machine ISA and supports shared virtual memory with the host CPU.
- A NoMali GPU model. gem5 comes with an integrated NoMali GPU model that is compatible with the Linux and Android GPU driver stack, and thus removes the need for software rendering. The NoMali GPU does not produce any output, but ensures that CPU-centric experiments produce representative results.
- Event-driven memory system. gem5 features a detailed, event-driven memory system including caches, crossbars, snoop filters, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4/5, DDR3/4, GDDR5, HBM1/2/3, HMC, WideIO1/2. The components can be arranged flexibly, e.g., to model complex multi-level non-uniform cache hierarchies with heterogeneous memories.
- A trace-based CPU model that plays back elastic traces, which are dependency and timing annotated traces generated by a probe attached to the out-of-order CPU model. The focus of the Trace CPU model is to achieve memory-system (cache-hierarchy, interconnects and main memory) performance exploration in a fast and reasonably accurate way instead of using the detailed CPU model.
- Homogeneous and heterogeneous multi-core. The CPU models and caches can be combined in arbitrary topologies, creating homogeneous, and heterogeneous multi-core systems. A MOESI snooping cache coherence protocol keeps the caches coherent.
- Multiple ISA support. gem5 decouples ISA semantics from its CPU models, enabling effective support of multiple ISAs. Currently gem5 supports the Alpha, ARM, SPARC, MIPS, POWER, RISC-V and x86 ISAs. See Supported Architectures for more information.
- Full-system capability.
- Alpha: gem5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
- ARM: gem5 can model up to 64 (heterogeneous) cores of a Realview ARM platform, and boot unmodified Linux and Android with a combination of in-order and out-of-order CPUs. The ARM implementation supports 32 or 64-bit kernels and applications.
- SPARC: The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
- x86: The gem5 simulator supports a standard PC platform
- Multi-system capability. Multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
- Power and energy modeling. gem5’s objects are arranged in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynamic Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See how to run your own DVFS experiments.
- Co-simulation with SystemC. gem5 can be included in a SystemC simulation, effectively running as a thread inside the SystemC event kernel, and keeping the events and timelines synchronized between the two worlds. This functionality enables the gem5 components to interoperate with a wide range of System on Chip (SoC) component models, such as interconnects, devices and accelerators. A wrapper for SystemC Transaction Level Modelling (TLM) is provided.
Download
- The canonical version of gem5 is available at https://gem5.googlesource.com/. (See the Repository page for details.) Auxiliary files are available on on our Download page.
Additional details
- Application-only support. In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with Linux emulation.
- Platforms. The gem5 simulator runs on most operating systems (Linux, MacOS X, OpenBSD) and architectures (x86, x86-64, ARM, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC and/or clang.
- Licensing. The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources.
Documentation
There are several sources of documentation for gem5:
- The most detailed and up-to-date documentation is on this wiki. The documentation page serves as a general table of contents for these pages. There is also a list of Frequently Asked Questions.
- The Mailing Lists archives contain lots of useful information. Please look at the sidebar for mailing list subscription information.
- We have archived material from various tutorials, which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere. There are also a number of recent workshops outlining ongoing work, such as the full-day workshop at ISCA-42.
- A higher-level overview of gem5 can be found in our article The gem5 Simulator from the May 2011 issue of ACM SIGARCH Computer Architecture News. If you use gem5 in your research, we would appreciate a citation to this paper in any publications you produce.
- The gem5 code is (somewhat sparsely) commented with doxygen comments. You can browse the doxygen-generated documentation here.
Publications
A list of publications using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5.
If you use gem5 in your research, we would appreciate a citation to, The gem5 Simulator, from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce. In addition, please cite the specific features of gem5 that you are using as part of your research.
Acknowledgments
The gem5 simulator has been developed with generous support from several sources, including the National Science Foundation, AMD, ARM, Hewlett-Packard, IBM, Intel, MIPS, and Sun. Individuals working on gem5 have also been supported by fellowships from Intel, Lucent, and the Alfred P. Sloan Foundation. This material is based upon work supported by the National Science Foundation under the following grants: CCR-0105503, CCR-0219640, CCR-0324878, EAI/CNS-0205286, and CCR-0105721.
Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF) or any other sponsor.
