Difference between revisions of "X86 microop ISA"

From gem5
Jump to: navigation, search
Line 1: Line 1:
[[Register Ops (X86 Microops)|Register Ops]]
+
== Register Ops ==
  
[[Load/Store Ops (X86 Microops)|Load/Store Ops]]
+
=== Addition and subtraction ===
  
[[Load immediate Op (x86 Microops)|Load immediate Op]]
+
==== Add ====
 +
 
 +
==== Adc ====
 +
 
 +
==== Sub ====
 +
 
 +
==== Sbb ====
 +
 
 +
=== Multiplication and division ===
 +
 
 +
==== Mul1s ====
 +
 
 +
==== Mul1u ====
 +
 
 +
==== Mulel ====
 +
 
 +
==== Muleh ====
 +
 
 +
==== Div1 ====
 +
 
 +
==== Div2 ====
 +
 
 +
==== Divq ====
 +
 
 +
==== Divr ====
 +
 
 +
=== Logic ===
 +
 
 +
==== Or ====
 +
 
 +
==== And ====
 +
 
 +
==== Xor ====
 +
 
 +
=== Shifts and Rotates ===
 +
 
 +
==== Sll ====
 +
 
 +
==== Srl ====
 +
 
 +
==== Sra ====
 +
 
 +
==== Ror ====
 +
 
 +
==== Rcr ====
 +
 
 +
==== Rol ====
 +
 
 +
==== Rcl ====
 +
 
 +
=== Data transfer and conversion ===
 +
 
 +
==== Mov ====
 +
 
 +
==== Sext ====
 +
 
 +
==== Zext ====
 +
 
 +
==== Ruflag ====
 +
 
 +
==== Ruflags ====
 +
 
 +
==== Wruflags ====
 +
 
 +
=== Control transfer ===
 +
 
 +
==== Br ====
 +
 
 +
==== Rdip ====
 +
 
 +
==== Wrip ====
 +
 
 +
== Load/Store Ops ==
 +
 
 +
== Load immediate Op ==

Revision as of 15:30, 27 September 2007

Register Ops

Addition and subtraction

Add

Adc

Sub

Sbb

Multiplication and division

Mul1s

Mul1u

Mulel

Muleh

Div1

Div2

Divq

Divr

Logic

Or

And

Xor

Shifts and Rotates

Sll

Srl

Sra

Ror

Rcr

Rol

Rcl

Data transfer and conversion

Mov

Sext

Zext

Ruflag

Ruflags

Wruflags

Control transfer

Br

Rdip

Wrip

Load/Store Ops

Load immediate Op