Unaligned memory accesses

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I believe real hardware takes care of memory alignment by issuing two loads or stores if necessary from the same instruction in the load/store queue. The result is combined after the data gets back as part of the load/store and things continue. That doesn't seem to fit very well with m5 which assumes aligned accesses and causes problems if it receives something else. ptlsim handles things by having two different versions of every memory operation which do the low and high portions of an access and then glue it together. There are probably complications there with goofy segmentation and paging, and it doesn't seem like it would be very accurate performance wise.