Difference between revisions of "Status Matrix"

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(add note about x86 locked accesses not working on classic caches in timing mode)
(→‎ISA Support Matrices)
 
(25 intermediate revisions by 5 users not shown)
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== Notes ==
 
== Notes ==
 +
Below [[Classic Memory System | Classic]] and [[Ruby]] refers to the two memory systems that we have in gem5. [[MI_example|MI]], [[MESI Two Level | MESI]] and [[Ruby#SLICC + Coherence protocols: | MOESI]] (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: [[SimpleCPU | AtomicSimple]], [[SimpleCPU | TimingSimple]], [[InOrder]] and [[O3CPU | O3]].
  
 
Numbers in the squares below refer to the following notes:
 
Numbers in the squares below refer to the following notes:
Line 21: Line 22:
 
# Ruby does not support atomic-mode accesses
 
# Ruby does not support atomic-mode accesses
 
# The MI_example protocol cannot support LL/SC semantics
 
# The MI_example protocol cannot support LL/SC semantics
−
# Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
 
−
# ARM MP does not support booting with caches, but works otherwise.  You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
 
 
# Classic caches do not support x86 locked (atomic RMW) accesses.  The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
 
# Classic caches do not support x86 locked (atomic RMW) accesses.  The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
  
 
== ISA Support Matrices ==
 
== ISA Support Matrices ==
 +
 +
'''''THIS PAGE WAS LAST UPDATED IN 2015. IT IS LIKELY OUT OF DATE. USE THIS AS A GUIDELINE.'''''
  
 
=== Alpha ===
 
=== Alpha ===
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!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
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| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
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|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
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| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
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| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
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| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
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|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
Line 138: Line 139:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
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| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
Line 156: Line 157:
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
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| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 2
 
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
 
|-
 
|-
 
|}
 
|}
  
−
=== x86 ===
+
=== ARM ===
  
 
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
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!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
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|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
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| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 233: Line 234:
 
|-
 
|-
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
−
| style="background: yellow;" |
 
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: red; color: white" | Note 5
+
| style="background: green; color: white" |
−
| style="background: yellow;" |
+
| style="background: red; color: white"| Note 2
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
−
| style="background: yellow;" |
 
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: green; color: white" |
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
−
| style="background: yellow;" |
 
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: red; color: white" | Note 5
+
| style="background: green; color: white" |
−
| style="background: yellow;" |
+
| style="background: red; color: white"| Note 2
−
| style="background: yellow;" |
+
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
−
| style="background: yellow;" |
 
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
−
| style="background: red; color: white" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
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| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: red; color: white" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
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|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: red; color: white" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
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| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: red; color: white" |
+
| style="background: green; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
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| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
−
!rowspan="2"|SE
+
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: yellow; color: white" |
+
| style="background: green; color: white" |
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white"|
 +
| style="background: orange; color: white" |
 +
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 +
|-
 +
|multi
 +
| style="background: green; color: white" |
 +
| style="background: red; color: white"| Note 2
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
−
|-
 
−
|multiprocessor
 
−
| style="background: red; color: white" | Note 5
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: red; color: white" |
+
| style="background: green; color: white" |
−
| style="background: red; color: white" |
+
| style="background: red; color: white"| Note 2
−
| style="background: red; color: white" |
+
| style="background: orange; color: white"|
−
| style="background: red; color: white" |
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" |
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" |
+
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: red; color: white" | Note 5
+
| style="background: green; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white"| Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
 
|-
 
|-
 
|}
 
|}
  
−
=== ARM ===
+
=== x86 ===
  
 
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
 
{| border="1" class="wikitable" align=center style="background:#B0C4DE;"
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!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 353: Line 354:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: green; color: white" |
+
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 363: Line 364:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" |
+
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 372: Line 373:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: green; color: white" |
+
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 380: Line 381:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" | Note 4
+
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 389: Line 390:
 
|-
 
|-
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
−
!rowspan="2"|SE  
+
!rowspan="2"|SE
−
|uniprocessor
+
|uni
−
| style="background: green; color: white" |
+
| style="background: yellow;" |
−
| style="background: orange; color: white"|
+
| style="background: yellow;" |
−
| style="background: orange; color: white"|
+
| style="background: yellow;" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow;" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" |
+
| style="background: yellow;" | Note 3
−
| style="background: red; color: white"| Note 2
+
| style="background: yellow;" |
−
| style="background: orange; color: white"|
+
| style="background: yellow;" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow;" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 +
| style="background: yellow;" | Note 3
 +
| style="background: yellow;" |
 +
| style="background: yellow;" |
 
| style="background: green; color: white" |
 
| style="background: green; color: white" |
−
| style="background: orange; color: white"|
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white"|
+
| style="background: yellow;" |
−
| style="background: orange; color: white" |
 
−
| style="background: orange; color: white" |
 
−
| style="background: orange; color: white" |
 
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" | Note 4
+
| style="background: yellow;" | Note 3
−
| style="background: red; color: white"| Note 2
+
| style="background: yellow;" |
−
| style="background: orange; color: white"|
+
| style="background: yellow;" |
−
| style="background: orange; color: white" |
+
| style="background: green; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow;" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE
 
!rowspan="2"|SE
−
|uniprocessor
+
|uni
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 433: Line 434:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
Line 442: Line 443:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 450: Line 451:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 458: Line 459:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
−
!rowspan="2"|SE  
+
!rowspan="2"|SE
−
|uniprocessor
+
|uni
−
| style="background: green; color: white" |
+
| style="background: yellow;" |
−
| style="background: orange; color: white"|
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white"|
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" |
+
| style="background: yellow;" | Note 3
−
| style="background: red; color: white"| Note 2
+
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: green; color: white" |
+
| style="background: orange; color: white" | Note 3
−
| style="background: orange; color: white"|
+
| style="background: red; color: white" | Note 2
−
| style="background: orange; color: white"|
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
−
| style="background: orange; color: white" |
+
| style="background: yellow; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: green; color: white" | Note 4
+
| style="background: orange; color: white" | Note 3
−
| style="background: red; color: white"| Note 2
+
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: yellow; color: white" |
 
|-
 
|-
 
|}
 
|}
Line 501: Line 502:
 
!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 509: Line 510:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 519: Line 520:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 528: Line 529:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 536: Line 537:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 546: Line 547:
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: orange; color: white"|
 
| style="background: orange; color: white"|
Line 554: Line 555:
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: orange; color: white"|
 
| style="background: orange; color: white"|
Line 563: Line 564:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
Line 571: Line 572:
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 579: Line 580:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white"|
 
| style="background: red; color: white"|
Line 589: Line 590:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white"|
 
| style="background: red; color: white"|
Line 598: Line 599:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 606: Line 607:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 614: Line 615:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: yellow; color: white" |
+
| style="background: yellow;" |
 
| style="background: orange; color: white"|
 
| style="background: orange; color: white"|
 
| style="background: orange; color: white"|
 
| style="background: orange; color: white"|
Line 624: Line 625:
 
| style="background: orange; color: white" |
 
| style="background: orange; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: yellow; color: white" |
+
| style="background: yellow;" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: orange; color: white" |
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
Line 641: Line 642:
 
| style="background: red; color: white" |
 
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: red; color: white" |  
 
| style="background: red; color: white" |  
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
 
|-
 
|-
 
|}
 
|}
Line 657: Line 658:
 
!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 665: Line 666:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 675: Line 676:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 684: Line 685:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: red;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 692: Line 693:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: orange;" |
+
| style="background: red;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 702: Line 703:
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 710: Line 711:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 719: Line 720:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: red;" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: orange;" |
+
| style="background: red;" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 745: Line 746:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 754: Line 755:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 780: Line 781:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: purple; color: white" |
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
|-
 
−
!rowspan="2"|FS
 
−
|uniprocessor
 
−
| style="background: yellow;" |
 
−
| style="background: purple; color: white"|
 
−
| style="background: purple; color: white"|
 
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
!rowspan="2"|FS
−
| style="background: orange;" |
+
|uni
−
| style="background: red; color: white" | Note 3
+
| style="background: red;" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white"|
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white"|
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
 
|}
 
|}
Line 813: Line 814:
 
!colspan="6"|Memory System
 
!colspan="6"|Memory System
 
|-
 
|-
−
!rowspan="2"|Cpu Model
+
!rowspan="2"|Model
 
!rowspan="2"|System
 
!rowspan="2"|System
−
!rowspan="2"|Processor Count
+
!rowspan="2"|Count
 
!rowspan="2"|Classic
 
!rowspan="2"|Classic
 
!colspan="5"|Ruby
 
!colspan="5"|Ruby
Line 821: Line 822:
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|MI_example||MOESI_hammer||MESI_CMP_directory||MOESI_CMP_directory||MOESI_CMP_token
 
|-
 
|-
−
!rowspan="4"|Atomic
+
!rowspan="4"|AtomicSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 831: Line 832:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 840: Line 841:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: red;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 848: Line 849:
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: orange;" |
+
| style="background: red;" |
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
 
| style="background: red; color: white" | Note 1
Line 858: Line 859:
 
!rowspan="4"|TimingSimple
 
!rowspan="4"|TimingSimple
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 866: Line 867:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 875: Line 876:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: yellow;" |
+
| style="background: red;" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: orange;" |
+
| style="background: red;" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|In-Order
+
!rowspan="4"|InOrder
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
−
| style="background: orange;" |
+
| style="background: red;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 901: Line 902:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: orange;" |
+
| style="background: red;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 910: Line 911:
 
|-
 
|-
 
!rowspan="2"|FS
 
!rowspan="2"|FS
−
|uniprocessor
+
|uni
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white"|
+
| style="background: red; color: white"|
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
−
| style="background: purple; color: white" |
+
| style="background: red; color: white" |
 
|-
 
|-
−
!rowspan="4"|o3
+
!rowspan="4"|O3
 
!rowspan="2"|SE  
 
!rowspan="2"|SE  
−
|uniprocessor
+
|uni
 
| style="background: yellow;" |
 
| style="background: yellow;" |
 
| style="background: purple; color: white"|
 
| style="background: purple; color: white"|
Line 936: Line 937:
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
|multi
 
| style="background: orange;" |
 
| style="background: orange;" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" | Note 2
−
| style="background: red; color: white" | Note 3
+
| style="background: purple; color: white" |
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
| style="background: red; color: white" | Note 3
 
−
|-
 
−
!rowspan="2"|FS
 
−
|uniprocessor
 
−
| style="background: yellow;" |
 
−
| style="background: purple; color: white"|
 
−
| style="background: purple; color: white"|
 
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
| style="background: purple; color: white" |
 
|-
 
|-
−
|multiprocessor
+
!rowspan="2"|FS
−
| style="background: orange;" |
+
|uni
−
| style="background: red; color: white" | Note 3
+
| style="background: red;" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white"|
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white"|
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
−
| style="background: red; color: white" | Note 3
+
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
|-
 +
|multi
 +
| style="background: red;" |
 +
| style="background: red; color: white" | Note 2
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 +
| style="background: red; color: white" |
 
|-
 
|-
 
|}
 
|}

Latest revision as of 17:06, 23 February 2018

The follow six tables describe the current state of component combinations in gem5.

Color Key

Definitely does not work
Might work
Should work
Definitely works
Unknown

Notes

Below Classic and Ruby refers to the two memory systems that we have in gem5. MI, MESI and MOESI (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: AtomicSimple, TimingSimple, InOrder and O3.

Numbers in the squares below refer to the following notes:

  1. Ruby does not support atomic-mode accesses
  2. The MI_example protocol cannot support LL/SC semantics
  3. Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.

ISA Support Matrices

THIS PAGE WAS LAST UPDATED IN 2015. IT IS LIKELY OUT OF DATE. USE THIS AS A GUIDELINE.

Alpha

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 2
FS uni
multi Note 2
InOrder SE uni
multi Note 2
FS uni
multi Note 2
O3 SE uni
multi Note 2
FS uni
multi Note 2

ARM

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 2
FS uni
multi Note 2
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni Note 2
multi Note 2

x86

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi Note 3
FS uni Note 3
multi Note 3
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 3 Note 2
FS uni Note 3 Note 2
multi Note 3 Note 2

SPARC

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2

PowerPC

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2

MIPS

Processor Memory System
Model System Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
AtomicSimple SE uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
FS uni Note 1 Note 1 Note 1 Note 1 Note 1
multi Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uni
multi
FS uni
multi
InOrder SE uni
multi
FS uni
multi
O3 SE uni
multi Note 2
FS uni
multi Note 2
Retrieved from "http://repo.m5sim.org/wiki/index.php?title=Status_Matrix&oldid=8337"