Difference between revisions of "Status Matrix"

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(Factor text out into numbered notes)
(add note about x86 locked accesses not working on classic caches in timing mode)
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# Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
 
# Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
 
# ARM MP does not support booting with caches, but works otherwise.  You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
 
# ARM MP does not support booting with caches, but works otherwise.  You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
 +
# Classic caches do not support x86 locked (atomic RMW) accesses.  The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
  
 
== ISA Support Matrices ==
 
== ISA Support Matrices ==
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| style="background: red; color: white" | Note 5
 
| style="background: red; color: white" | Note 3
 
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| style="background: red; color: white" | Note 3
 
| style="background: red; color: white" | Note 3
 
| style="background: red; color: white" | Note 3
 
| style="background: red; color: white" | Note 3

Revision as of 20:55, 18 September 2011

The follow six tables describe the current state of component combinations in gem5.

Color Key

Definitely does not work
Might work
Should work
Definitely works
Unknown

Notes

Numbers in the squares below refer to the following notes:

  1. Ruby does not support atomic-mode accesses
  2. The MI_example protocol cannot support LL/SC semantics
  3. Ruby does not support probing the O3 LSQ to enforce non-weak consistency models
  4. ARM MP does not support booting with caches, but works otherwise. You can boot without caches then switch to running with caches using either a checkpoint/resume or on-line CPU switchover.
  5. Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.

ISA Support Matrices

Alpha

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor Note 2
FS uniprocessor
multiprocessor Note 2
In-Order SE uniprocessor
multiprocessor Note 2
FS uniprocessor
multiprocessor Note 2
o3 SE uniprocessor
multiprocessor Note 2 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 2 Note 3 Note 3 Note 3 Note 3

x86

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor Note 5
FS uniprocessor
multiprocessor Note 5
In-Order SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
o3 SE uniprocessor
multiprocessor Note 5 Note 3 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 5 Note 3 Note 3 Note 3 Note 3 Note 3

ARM

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 4 Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor Note 2
FS uniprocessor
multiprocessor Note 4 Note 2
In-Order SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
o3 SE uniprocessor
multiprocessor Note 2 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 4 Note 2 Note 3 Note 3 Note 3 Note 3

SPARC

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
In-Order SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
o3 SE uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3

PowerPC

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
In-Order SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
o3 SE uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3

MIPS

Processor Memory System
Cpu Model System Processor Count Classic Ruby
MI_example MOESI_hammer MESI_CMP_directory MOESI_CMP_directory MOESI_CMP_token
Atomic SE uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
FS uniprocessor Note 1 Note 1 Note 1 Note 1 Note 1
multiprocessor Note 1 Note 1 Note 1 Note 1 Note 1
TimingSimple SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
In-Order SE uniprocessor
multiprocessor
FS uniprocessor
multiprocessor
o3 SE uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3
FS uniprocessor
multiprocessor Note 3 Note 3 Note 3 Note 3 Note 3
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