Difference between revisions of "Projects"
From gem5
(Created page with "Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5.") |
|||
| Line 1: | Line 1: | ||
Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5. | Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5. | ||
| + | |||
| + | = MV5= | ||
| + | * MV5 is a reconfigurable simulator for heterogeneous multicore architectures. It is based on M5v2.0 beta 4. | ||
| + | * Typical usage: simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy. | ||
| + | * Research projects based on MV5 have been published in ISCA'10, ICCD'09, and IPDPS'10. | ||
| + | === Features === | ||
| + | * Single-Instruction, Multiple-Threads (SIMT) cores | ||
| + | * Directory-based Coherence Cache: MESI/MSI. (Not based on gem) | ||
| + | * Interconnect: Fully connected and 2D Mesh. (Not based on gem) | ||
| + | * Threading API/library in system emulation mode (No support for full-system simulation. A benchmark suite using the thread API is provided) | ||
| + | === Resources === | ||
| + | * Home Page: [https://sites.google.com/site/mv5sim/home] | ||
| + | * Tutorial at ISPASS '11: [https://sites.google.com/site/mv5sim/tutorial] | ||
| + | * Google group: [http://groups.google.com/group/mv5sim] | ||
Revision as of 23:21, 17 June 2011
Below is a list of projects that are based on gem5, are extensions of gem5, or use gem5.
MV5
- MV5 is a reconfigurable simulator for heterogeneous multicore architectures. It is based on M5v2.0 beta 4.
- Typical usage: simulating data-parallel applications on SIMT cores that operate over directory-based cache hierarchies. You can also add out-of-order cores to have a heterogeneous system, and all different types of cores can operate under the same address space through the same cache hierarchy.
- Research projects based on MV5 have been published in ISCA'10, ICCD'09, and IPDPS'10.
Features
- Single-Instruction, Multiple-Threads (SIMT) cores
- Directory-based Coherence Cache: MESI/MSI. (Not based on gem)
- Interconnect: Fully connected and 2D Mesh. (Not based on gem)
- Threading API/library in system emulation mode (No support for full-system simulation. A benchmark suite using the thread API is provided)
