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The M5 Simulator System
A modular platform for computer system architecture research


  • M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.



  • The current public release of M5 is available at (See the Repository page for details.) Auxiliary files are available on on our Download page. Please look at the sidebar for links to file bugs and for mailing list subscription information.

Key features

  • Pervasive object orientation. Major simulation structures (CPUs, busses, caches, etc.) are represented as objects, both externally and internally. M5's configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. M5's internal object orientation (using C++) provides in addition to the usual software engineering advantages.
  • Multiple interchangeable CPU models. M5 currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an out-of-order SMT-capable CPU; and a random memory-system tester. The first two models use a common high-level ISA description.
  • Event-driven memory system. M5 features a detailed, event-driven memory system including non-blocking caches and split-transaction busses. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; M5 currently includes a simple snooping cache coherence protocol.
  • Multiple ISA support. M5 decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs. M5 currently supports the Alpha, SPARC, MIPS, and ARM ISAs, with x86 support in progress. See Supported Architectures for more information.
  • Full-system capability.
    • Alpha: M5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
    • SPARC: M5 models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
    • MIPS/ARM/x86: In progress
  • Multiprocessor / multi-system capability. Thanks to M5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping bus-based coherence protocol supported by the caches, M5 can model symmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.

Additional details

  • Application-only support. In application-only (non-full-system) mode, M5 can execute a variety of architecture/OS binaries with OS emulation or SimpleScalar Alpha EIO trace files.
  • Platforms. M5 runs on most operating systems (Linux, MacOS X, Solaris, OpenBSD, Cygwin) and architectures (x86, x86-64, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC. Alpha binaries to run on M5 (including the full Linux kernel) can be built on x86 systems using gcc-based cross-compilation tools, so no Alpha hardware is needed to make full use of M5.
  • Licensing. M5 is being released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of M5 derived from other sources are also subject to the licensing restrictions of the original sources (notably SimpleScalar).
  • Provenance. Portions of M5 (EIO trace support and parts of our old obsolete detailed CPU model) were derived from SimpleScalar. These portions are released separately under the SimpleScalar license. We have a new detailed CPU model that eliminates any need for the SimpleScalar code unless you use EIO traces. We are also grateful to the SimOS and SimOS/Alpha developers, as SimOS/Alpha was an invaluable reference platform during our development of full-system mode.


There are several sources of documentation for M5:

  • We have archived material from various tutorials, which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere.
  • A higher-level overview of M5 can be found in our article The M5 Simulator: Modeling Networked Systems from the July/Aug 2006 issue of IEEE Micro. If you use M5 in your research, we would appreciate a citation to this paper in any publications you produce.
  • The M5 code is (somewhat sparsely) commented with doxygen comments. You can browse the doxygen-generated documentation here.


A list of publications using the M5 simulator is also available. Please append to the list if you publish a paper using M5.


The M5 simulator is being developed with generous support from several sources, including the National Science Foundation, Hewlett-Packard, Intel, IBM, MIPS, and Sun. Individuals working on M5 have also been supported by an Intel Fellowship (Nate Binkert), a Lucent Fellowship (Lisa Hsu), and a Sloan Research Fellowship (Steve Reinhardt).

This material is based upon work supported by the National Science Foundation under Grant Nos. CCR-0105503 and CCR-0219640. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).

Why is it called M5?