Difference between revisions of "InOrder Pipeline Stages"
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Revision as of 18:00, 12 January 2010
Pipeline Stages
In it's most basic incarnation, the In-Order model models a 5-stage pipeline.
The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the following stages:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Register Write Back (WB)
Relevant source files:
- first_stage.[hh,cc]
- pipeline_stage.[hh,cc]
