Difference between revisions of "InOrder Pipeline Stages"

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* pipeline_traits.[hh,cc]
 
* pipeline_traits.[hh,cc]
 
* cpu.[hh,cc]
 
* cpu.[hh,cc]
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== Interstage Communication ==
  
 
== Pipeline Processing ==
 
== Pipeline Processing ==

Revision as of 14:52, 13 January 2010

Overview

Relevant source files:

  • first_stage.[hh,cc]
  • pipeline_stage.[hh,cc]
  • pipeline_traits.[hh,cc]
  • cpu.[hh,cc]

Interstage Communication

Pipeline Processing

First Stage

Implementations

In it's most basic incarnation, the In-Order model models a 5-stage pipeline.

The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the following stages:

  • Instruction Fetch (IF)
  • Instruction Decode (ID)
  • Execute (EX)
  • Memory Access (MEM)
  • Register Write Back (WB)

Pipeline Customization

Stage Instantiation

Adding Your Own Stage

  • Python Configuration
  • Instruction Schedule Information