Difference between revisions of "InOrder Pipeline Stages"
From gem5
(Created page with '== Pipeline Stages == In it's most basic incarnation, the In-Order model models a 5-stage pipeline. The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the follow…') |
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− | == Pipeline | + | == Overview == |
+ | |||
+ | |||
+ | '''Relevant source files:''' | ||
+ | * first_stage.[hh,cc] | ||
+ | * pipeline_stage.[hh,cc] | ||
+ | * pipeline_traits.[hh,cc] | ||
+ | * cpu.[hh,cc] | ||
+ | |||
+ | == Pipeline Processing == | ||
+ | |||
+ | |||
+ | == First Stage == | ||
+ | |||
+ | |||
+ | == Implementations == | ||
In it's most basic incarnation, the In-Order model models a 5-stage pipeline. | In it's most basic incarnation, the In-Order model models a 5-stage pipeline. | ||
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* Register Write Back (WB) | * Register Write Back (WB) | ||
− | + | == Pipeline Customization== | |
− | * | + | === Stage Instantiation === |
− | * | + | === Adding Your Own Stage === |
+ | *Python Configuration | ||
+ | *Instruction Schedule Information |
Revision as of 16:20, 13 January 2010
Contents
Overview
Relevant source files:
- first_stage.[hh,cc]
- pipeline_stage.[hh,cc]
- pipeline_traits.[hh,cc]
- cpu.[hh,cc]
Pipeline Processing
First Stage
Implementations
In it's most basic incarnation, the In-Order model models a 5-stage pipeline.
The 5-stage pipeline is based on the 5-stage MIPS pipeline and has the following stages:
- Instruction Fetch (IF)
- Instruction Decode (ID)
- Execute (EX)
- Memory Access (MEM)
- Register Write Back (WB)
Pipeline Customization
Stage Instantiation
Adding Your Own Stage
- Python Configuration
- Instruction Schedule Information