Difference between revisions of "InOrder Instruction Schedules"

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= Instruction Schedules & Pipeline Definitions =
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== Instruction Schedules & Pipeline Definitions Overview ==
== Overview ==
 
 
Instruction scheduling is divided into a ''front-end schedule'' (IF and ID), which is uniform for all the instructions, and a ''back-end schedule'', which varies across the different instructions.
 
Instruction scheduling is divided into a ''front-end schedule'' (IF and ID), which is uniform for all the instructions, and a ''back-end schedule'', which varies across the different instructions.
  

Revision as of 22:01, 19 January 2010

Instruction Schedules & Pipeline Definitions Overview

Instruction scheduling is divided into a front-end schedule (IF and ID), which is uniform for all the instructions, and a back-end schedule, which varies across the different instructions.


Relevant source files:

  • pipeline_traits.[hh,cc]
  • cpu.[hh,cc]

Schedule Entries

Front-End Schedules

Key Parameters

Front-end Schedule Example

  • Front-end Schedule
    • The front-end schedule comprises of the IF and ID stages
      • IF
        • NPC is updated by the Fetch unit
        • Instruction fetch from the I-Cache is initiated
      • ID
        • Instruction fetch is completed by I-Cache
        • Instruction decode is performed by the Decode unit
        • Branch prediction is performed by the BPred unit
        • Target PC is updated by the Fetch unit

Back-end Schedule

Key Parameters

Back-end Schedule Example

  • Back-end Schedule
    • The back-end schedule comprises of the ID, EX, MEM, and WB stages
      • ID
        • For non-store instructions, the source registers, if any, are read by the RF Manager
        • For load instructions, address generation is performed by the AGEN unit and data read from the D-Cache is initiated
        • The rest of the instructions are executed in the execution units
          • Single cycle operations are sent to the integer EXU
          • Execution is initiated for the multicycle/pipelined operations
      • EX
        • Execution is finished for the multicycle/pipelined operations
        • For load instructions, data read from the D-Cache is completed
        • For store instructions, the following tasks are performed
          • The source registers are read by the RF manager
          • Address generation is performed by the AGen unit
          • Data write into the D-Cache is initiated
      • MEM
        • For store instructions, data write into the D-Cache is completed
      • WB
        • Destination registers are written into by the RF manager
        • The instruction is graduated by the Grad unit