How to implement an ISA

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Move out of isa?


ISA specific fault classes to be used in the ISA.

Functions I'd like to get rid of

  • genMachineCheckFault
  • genAlignmentFault


Interrupts class

Interrupt Level

Shouldn't be capitalized. Gets a request to set the interrupt level and returns what the interrupt level was actually set to.


Request that an interrupt happen. Like asserting the interrupt line.


Request that an interrupt not happen. Like deasserting a level triggered interrupt line.


Breaks naming convention. Clear all interrupts


Breaks naming convention. Not sure if this is right. Check to see if there are any interrupts pending


Get an interrupt fault object to invoke. The Interrupts object should internally prioritize interrupts so that they are handled in the right order.


Breaks naming convention. Don't remember what this does. Need to find the email from Ali.


Breaks naming convention. Returns the vector which describes the pending(?) interrupts in SPARC which is available as a (memory mapped?) register. This function panics in anything currently implemented other than SPARC, and it breaks the abstraction of the Interrupts object. Its existence allows necessary communication between two ISA specific components but goes through the ISA agnostic cpu. An argument for this function is that the cpu may need to modify the value returned by this function, so it needs to be able to intercept values and change them. This -really- breaks the abstraction of the Interrupts object by forcing the cpu to know what the vector means and what values are appropriate. This function needs to go away.


Functions to serialize and unserialize the state in the Interrupts object.



Not sure if this is right The number of bytes in a machine instruction? If that's the case, this doesn't make sense for x86 and may need to be handled differently.

Set endianness

A "using" directive which selects which endianness conversion functions are available.

delay slot define

A preprocessor define which sets whether that architecture has delay slots. This needs to go away.


A machine instruction which encodes a noop


Offsets which separate the different register types from one another in a flattened indexing space. It would be nice to phase these out.


The integer register which is defined by the architecture to always contain the value zero. Not all ISAs actually have such a register, so this needs to be done differently. This is simultaneously used as the offset of the integer zero register and the floating point zero register. This is correct in Alpha, but SPARC doesn't have a zero floating point register, and not all architectures will necessarily have the same index for both registers.

ABI significant register indices

It's not clear how these should be defined for architectures like x86 which keep some of these values exclusively on the stack.

  • StackPointerReg
  • ReturnAddressReg
  • ReturnValueReg
  • FramePointerReg
  • ArgumentReg0
  • ArgumentReg1
  • ArgumentReg2
  • ArgumentReg3
  • ArgumentReg4
  • ArgumentReg5


Second syscall return register


Maybe have the isa parser generate this value? Maximum number of source registers used by any instruction.


Maybe have the isa parser generate this value? Maximum number of destination registers used by any instruction.

LogVMPageSize, VMPageSize

Describes the size of a virtual memory page. Where is this used outside of translation? Where is translation not ISA specific? If there is no such place, maybe this should be defined internally to the ISA.

SegKPMEnd SegKPBase

Not sure what these are for. If they only make sense for one ISA or are used only in ISA specific places, they might not need to be part of the ISA interface

PageShift PageBytes

Not sure how this is different from VMPageSize and LogVMPageSize respectively.


The number of bits a PC value should be shifted in order to provide a compacted instruction addressing space. This makes no sense for x86 or any other variable instruction width ISA.


Prototype for the decodeInst function. Maybe this should be generated automatically? Not a big deal.

Full system stuff


Yes, a mask for the address used by loads, but to produce an address with what properties and why?

TLB stuff

Tlbs are ISA specific, so it's probably a good idea to put these in a new ISA internal header file, or in the existing tlb.hh.


This might belong in sparc_traits.hh (SPARC specific ISA parameters), or in interrupt.hh. There should be an alpha_traits.hh for analogous Alpha specific ISA parameters


Not sure


handleLockedRead handleLockedWrite

Not sure what these do, although I'm sure it has to do with LL/SC.


handleIprRead handleIprWrite

These are for handling accesses to memory mapped registers. I believe IPR is an Alpha-ism and a different name might be more appropriate. Are these called from anywhere outside of ISA specific code? If not, they should be moved out of the ISA interface.


Need to document exactly what this does and how. Defines an isa specific process object.


getTC setTC

These should both be eliminated. A better mechanism should be used to attach a predecoder to a thread context, perhaps just passing one in to relevant functions.


Feed more bytes to the predecoder.


Returns whether or not the predecoder needs more bytes, or in other words, whether you -don't- have left over data to start working with immediately.


Returns whether a whole ExtMachInst has been generated and is ready to be used.


Returns the ExtMachInst the predecoder has generated.