Difference between revisions of "Google Summer of Code"
From gem5
(New page: # ARM ISA #* Not realistic # Real F/S In-order core #* Kevin has one that works to some degree in SE, it doesn't have functional units yet, but it does have variable latency stages and suc...) |
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# Real F/S In-order core | # Real F/S In-order core | ||
#* Kevin has one that works to some degree in SE, it doesn't have functional units yet, but it does have variable latency stages and such | #* Kevin has one that works to some degree in SE, it doesn't have functional units yet, but it does have variable latency stages and such | ||
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# Fast Simple Core | # Fast Simple Core | ||
#* This largely disregards all the compartmentalization we've done. It touches a lot of things, so the time to start being productive would be high | #* This largely disregards all the compartmentalization we've done. It touches a lot of things, so the time to start being productive would be high | ||
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# Instruction page decode cache | # Instruction page decode cache | ||
#* Kinda goes along with the fast simple core, but i think it's a more manageable task. Clearing it is as simple as looking for flush instructions in sparc and the correct pal trap in alpha | #* Kinda goes along with the fast simple core, but i think it's a more manageable task. Clearing it is as simple as looking for flush instructions in sparc and the correct pal trap in alpha | ||
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# Sampling/checkpointing/restarting | # Sampling/checkpointing/restarting | ||
#* Testing, fixing, etc... Not exactly exciting work | #* Testing, fixing, etc... Not exactly exciting work | ||
| − | # Write a PLI interface to connect Verilog CPUs to the memory system | + | # Write a PLI interface to connect Verilog CPUs to the memory system. |
# Sampling/fast-forwarding techniques (making sure ours works, maybe adding in some new ones) | # Sampling/fast-forwarding techniques (making sure ours works, maybe adding in some new ones) | ||
# Different cache models (different replacement policies, etc.; would allow them to do some research into it, maybe get some work done for Lisa) | # Different cache models (different replacement policies, etc.; would allow them to do some research into it, maybe get some work done for Lisa) | ||
# Different prefetcher models (expand on what Ron has, also can do some research into it) | # Different prefetcher models (expand on what Ron has, also can do some research into it) | ||
# Flash memory device model? (seems popular nowadays) | # Flash memory device model? (seems popular nowadays) | ||
Revision as of 08:14, 11 March 2008
- Real F/S In-order core
- Kevin has one that works to some degree in SE, it doesn't have functional units yet, but it does have variable latency stages and such
- Korey has one he did at MIPS, I don't know about it's features, but it's SE only as well
- Fast Simple Core
- This largely disregards all the compartmentalization we've done. It touches a lot of things, so the time to start being productive would be high
- Instruction page decode cache
- Kinda goes along with the fast simple core, but i think it's a more manageable task. Clearing it is as simple as looking for flush instructions in sparc and the correct pal trap in alpha
- Directory Protocol
- Not realistic
- SMT
- Fix O3 bugs/ Fix ROB Units
- It's a huge pile of code to understand before you get anywhere if they get that far
- Parallelize M5
- If only, but not realistic
- Are there any other benchmarks we want?
- That they could possible make work?
- Devices?
- Validate the DRAM model?
- Sampling/checkpointing/restarting
- Testing, fixing, etc... Not exactly exciting work
- Write a PLI interface to connect Verilog CPUs to the memory system.
- Sampling/fast-forwarding techniques (making sure ours works, maybe adding in some new ones)
- Different cache models (different replacement policies, etc.; would allow them to do some research into it, maybe get some work done for Lisa)
- Different prefetcher models (expand on what Ron has, also can do some research into it)
- Flash memory device model? (seems popular nowadays)
