Difference between revisions of "GPU Models"

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(AMD's Compute-GPU Model)
(GCN3 Based Simulation)
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== AMD's Compute-GPU Model ==
 
== AMD's Compute-GPU Model ==
 
=== GCN3 Based Simulation ===
 
=== GCN3 Based Simulation ===
===== ISCA 2018 Tutorial =====
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===== ISCA 2018 tutorial =====
A tutorial was held on June 2nd, 2018, in conjuction with the 45th International Symposium on Computer Architecture (ISCA). Our presentation can be found here: [[Media:AMD_gem5_APU_simulator_isca_2018_gem5_wiki.pptx | The AMD gem5 APU Simulator: Modeling GPUs Using the Machine ISA]].
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A tutorial was held on June 2nd, 2018, in conjuction with the 45th International Symposium on Computer Architecture (ISCA).
The GCN3 ISA is supported in [https://gem5.googlesource.com/amd/gem5/+/agutierr/master-gcn3-staging AMD's public pre-release gem5 repo] on the branch agutierr/master-gcn3-staging.
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Our presentation can be found here: [[Media:AMD_gem5_APU_simulator_isca_2018_gem5_wiki.pptx | The AMD gem5 APU Simulator: Modeling GPUs Using the Machine ISA]].
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The GCN3 ISA is supported in [https://gem5.googlesource.com/amd/gem5/+/agutierr/master-gcn3-staging AMD's public pre-release gem5 repo]
 +
on the branch agutierr/master-gcn3-staging.
  
 
===== Cloning the repository =====
 
===== Cloning the repository =====
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===== Building the simulator with GPU and GCN3 support =====
 
===== Building the simulator with GPU and GCN3 support =====
Currently, the GPU model only works with X86 and the VIPER protocol, which you can read about in the slides from AMD's 2018 ISCA tutorial.
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Currently, the GPU model only works with X86 and the VIPER protocol, which you can read about in the slides
To build gem5 with a GCN3-based GPU model included use the following command:
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from AMD's 2018 ISCA tutorial. To build gem5 with a GCN3-based GPU model included use the following command:
  
 
<code>scons -sQ -jN ./build/GCN3_X86/gem5.opt</code>
 
<code>scons -sQ -jN ./build/GCN3_X86/gem5.opt</code>
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===== Runtime software and toolchain =====
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In contrast to HSAIL execution, the GCN3 model does not rely on an emulated runtime (i.e., a simulator-specific
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implementation of the GPU runtime API). Instead, the model was designed with enough fidelity to run the userspace
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components of an off-the-shelf version of the Radeon Open Compute platform (ROCm). ROCm is an open platform from
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AMD that implements [http://www.hsafoundation.com/ Heterogeneous Systems Architecture (HSA)] principles. More
 +
information about the HSA standard can be found on the HSA Foundation's website.
 +
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The model currently only works
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with system-call emulation (SE) mode, therefore all kernel level driver functionality is modeled entirely within the
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SE mode layer of gem5. In particular, the emulated GPU driver supports the necessary <code>ioctl()</code> commands
 +
it receives from the userspace code. The source for the emulated GPU driver can be found in:
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* The GPU compute driver: <code>src/gpu-compute/gpu_compute_driver.[hh|cc]</code>
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* The HSA device driver: <code>src/dev/hsa/hsa_driver.[hh|cc]</code>
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The HSA driver code models the basic functionality for an HSA agent, which is any device that can be targeted by the HSA runtime and accepts Architected Query Language (AQL) packets. AQL packets are a standard format for all HSA agents, and are used primarily to initiate kernel launches on the GPU. The base <code>HSADriver</code> class holds a pointer to the HSA packet processor for the device, and defines the interface for any HSA device. An HSA agent does not have to be a GPU, it could be a generic accelerator, CPU, NIC, etc.
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The <code>GPUComputeDriver</code> derives from <code>HSADriver</code> and is a device-specific implementation of an <code>HSADriver</code>. It provides the implementation for GPU-specific <code>ioctl()</code> calls.
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====== Obtaining the compiler and userspace software stack ======
  
 
=== HSAIL Based Simulation ===
 
=== HSAIL Based Simulation ===

Revision as of 16:57, 5 July 2018

AMD's Compute-GPU Model

GCN3 Based Simulation

ISCA 2018 tutorial

A tutorial was held on June 2nd, 2018, in conjuction with the 45th International Symposium on Computer Architecture (ISCA). Our presentation can be found here: The AMD gem5 APU Simulator: Modeling GPUs Using the Machine ISA. The GCN3 ISA is supported in AMD's public pre-release gem5 repo on the branch agutierr/master-gcn3-staging.

Cloning the repository

To clone the repo with GCN3 support use the following command:

git clone https://gem5.googlesource.com/amd/gem5 -b agutierr/master-gcn3-staging

Building the simulator with GPU and GCN3 support

Currently, the GPU model only works with X86 and the VIPER protocol, which you can read about in the slides from AMD's 2018 ISCA tutorial. To build gem5 with a GCN3-based GPU model included use the following command:

scons -sQ -jN ./build/GCN3_X86/gem5.opt

Runtime software and toolchain

In contrast to HSAIL execution, the GCN3 model does not rely on an emulated runtime (i.e., a simulator-specific implementation of the GPU runtime API). Instead, the model was designed with enough fidelity to run the userspace components of an off-the-shelf version of the Radeon Open Compute platform (ROCm). ROCm is an open platform from AMD that implements Heterogeneous Systems Architecture (HSA) principles. More information about the HSA standard can be found on the HSA Foundation's website.

The model currently only works with system-call emulation (SE) mode, therefore all kernel level driver functionality is modeled entirely within the SE mode layer of gem5. In particular, the emulated GPU driver supports the necessary ioctl() commands it receives from the userspace code. The source for the emulated GPU driver can be found in:

  • The GPU compute driver: src/gpu-compute/gpu_compute_driver.[hh|cc]
  • The HSA device driver: src/dev/hsa/hsa_driver.[hh|cc]

The HSA driver code models the basic functionality for an HSA agent, which is any device that can be targeted by the HSA runtime and accepts Architected Query Language (AQL) packets. AQL packets are a standard format for all HSA agents, and are used primarily to initiate kernel launches on the GPU. The base HSADriver class holds a pointer to the HSA packet processor for the device, and defines the interface for any HSA device. An HSA agent does not have to be a GPU, it could be a generic accelerator, CPU, NIC, etc.

The GPUComputeDriver derives from HSADriver and is a device-specific implementation of an HSADriver. It provides the implementation for GPU-specific ioctl() calls.

Obtaining the compiler and userspace software stack

HSAIL Based Simulation

MICRO-48 Tutoral

A tutorial was held in conjunction with MICRO-48. We have made the slides available from our 2015 tutorial titled: The AMD gem5 APU Simulator: Modeling Heterogeneous Systems in gem5.

Emualted CL Runtime
OpenCL Compiler

CLOC is used to compile OpenCL kernels for use with gem5's GPU compute model. The most recent revision of CLOC that is known to work with gem5 is:

commit cf777856cfce86d11ea97c245992971159b85a4d

ARM's NoMali GPU Model

The NoMali GPU model models the interface used by ARM Mali GPUs. The model does not render or compute anything, but can be used to fake a GPU. This enables Android and ChromeOS experiments without software rendering which would otherwise make simulation results extremely misleading. It was presented in the 2015 gem5 User Workshop.

Getting started instructions are currently available for Android 4.4 (KitKat).