Difference between revisions of "Documentation"

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# [[SE Mode]]
 
# [[SE Mode]]
  
== CPUs and Execution ==
+
== Instruction Execution ==
 
# [[Execution Basics]]
 
# [[Execution Basics]]
 
# [[Architectural State]]
 
# [[Architectural State]]
 
# [[Address Translation]]
 
# [[Address Translation]]
# CPU Models
+
== CPU Models ==
## [[SimpleCPU | Simple CPU Model]]
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# [[SimpleCPU | Simple CPU Model]]
## [[O3CPU | Out-of-Order CPU Model]]
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# [[O3CPU | Out-of-Order CPU Model]]
## [[InOrder | In Order CPU Model]]
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# [[InOrder | In Order CPU Model]]
## [[Adding a New CPU Model]]
+
# [[Adding a New CPU Model]]
  
 
== ISA Implementations ==
 
== ISA Implementations ==

Revision as of 22:00, 10 April 2011

Getting Started

  1. Introduction - A quick introduction to gem5.
  2. Source Code - Information about the source code itself.
  3. External Dependencies - Things you'll need that aren't part of gem5 itself.
  4. Build System - How to run or modify gem5's build system.

Running M5

  1. Running M5 - Starting a simulation from the command line.
  2. Regression Tests - Running the regression tests.
  3. SimObjects - What SimObjects are and how they work.
  4. Configuration Scripts - This and the next section need to be merged.
  5. Simulation Scripts Explained
  6. Summary gem5 Capabilities

Workloads

  1. Getting a Cross Compiler
  2. m5ops - Instructions to control the simulation

Development

  1. Functional Testers
    1. directedtest
    2. memtest
    3. networktest
    4. rubytest
  2. Debugging
  3. Coding Style
  4. Tools and Contributing
  5. Source Code Documentation
  6. Commit Access

Infrastructure

  1. Events
  2. Statistics
  3. Utility Code
  4. Serialization

Memory System

  1. General Memory System
  2. Classic Memory System
  3. Ruby

Full System

  1. Devices
    1. IDE Devices
    2. NIC Devices
    3. Timers
    4. UARTs and serial terminals
  2. Disks and Disk Images
  3. Interrupts

Syscall Emulation

  1. SE Mode

Instruction Execution

  1. Execution Basics
  2. Architectural State
  3. Address Translation

CPU Models

  1. Simple CPU Model
  2. Out-of-Order CPU Model
  3. In Order CPU Model
  4. Adding a New CPU Model

ISA Implementations

  1. Multiple ISA Support
  2. ISA Parser
  3. Alpha Implementation
  4. ARM Implementation
  5. MIPS Implementation
  6. Power Implementation
  7. SPARC Implementation
  8. X86 Implementation
  9. Defining ISAs