Difference between revisions of "Defining ISAs (as of M5 2.0 beta 3)"

From gem5
Jump to: navigation, search
 
 
(21 intermediate revisions by the same user not shown)
Line 1: Line 1:
First, make sure you have basic understanding of the ISA description objects within the M5 framework. A good start is the [[CPU Models]] page.  
+
==Overview==
 +
First, make sure you have basic understanding of how an ISA description generates instructions within the M5 framework. A good start is the [[The M5 ISA description language]] page.  
  
The easiest way is to derive a new C++ class of your CPU Model from M5 CPU Models that are already defined and the easiest model to start with is probably the 'AtomicSimpleCPU' located in the 'm5/src/cpu/simple' directory.  
+
For this example, we will be constructing an ISA called MyISA which will just be a renamed version of the MIPS ISA. We will go through the steps of creating the files
 +
and configuration opions for an M5 ISA description.
  
For example, one could copy the files from the 'm5/src/cpu/simple' and place them in their own CPU directory: m5/src/cpu/my_cpu.
+
Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description will allow your MyISA
 +
architecture (analagous to ALPHA,MIPS,SPARC,etc.) to be plugged into System-Call Emulation (SE) and Full-System (FS) simulations of any M5 CPU Model.
  
'''After you create a separate directory for your code (e.g. 'm5/src/cpu/my_cpu'), there are a couple files that need to be updated:'''
+
== Syscall Emulation (SE) MyISA ==
*'''''m5/SConstruct''''': Add the name of your CPU model to the 'ALL_CPU_LIST'
 
  
*'''''m5/src/cpu/SConscript''''': Add your CPU model and the relevant files that need to be built in here
+
=== Creating the Files for MyISA ===
 +
The correct place to insert your ISA files in M5 is in the src/arch directory. In this directory, create another directory called 'myisa' to keep your code.
 +
For this example, we will copy the relevant files needed from the M5 MIPS ISA description.
 +
<pre>
 +
cd src/arch
 +
mkdir myisa
 +
cd myisa
 +
cp -r ../mips/*.hh ./
 +
cp -r ../mips/*.cc ./
 +
</pre>
 +
 
 +
The relevant files are as follows:
 +
* isa_traits.hh/cc - <explanation here>
 +
* regfile.hh/cc, regfile/* - <explanation here>
 +
* process.hh/cc -  <explanation here>
 +
* linux/* -  <explanation here>
 +
* isa/* -  <explanation here>
 +
* faults.hh/cc - <explanation here>
  
*'''''m5/src/cpu/static_inst.hh''''': Put a forward class declaration of your model in here
+
You need to make sure that all instances of MipsISA needs to be replaced with MyISA in the files.
 +
<pre>
 +
perl -pe s/Mips/My/g ????
 +
</pre>
  
*'''''m5/src/cpu/cpu_models.py''''': Add in CPU Model-specific information for the ISA Parser. The ISA Parser will use this when referring to the "Execution Context" for executing instructions. For instance, the AtomicSimpleCPU's instructions get all of their information from the actual CPU (since it's a 1 CPI machine). Thus, instructions only need to know the current state or "Execution Context" of the 'AtomicSimpleCPU' object. However, the instructions in a O3CPU needed to know the register values (& other state) only known to that current instruction so it's "Execution Context" is the O3DynInst object. (check out the [[The M5 ISA description language | ISA Description Language documentation]] page for more details)
+
=== Making M5 Recognize MyISA ===
 +
* m5/build_opts/MYISA_SE - Create this file that allows M5 to recognize MyISA as a Syscall Emulation build option. It's contents should contain:
 +
<pre>
 +
TARGET_ISA = 'myisa'
 +
FULL_SYSTEM = 0
 +
</pre>
  
*'''''m5/src/python/objects/my_cpu.py''''': Create a python file (e.g. MyCPU.py) so that your CPU can be recognized as a simulation object. A good example to follow is the file 'O3CPU.py'.
+
* m5/src/arch/isa_specific.hh - Edit this file by adding a constant for MyISA and then adding MyISA to the #define if/else structure.  
 +
<pre>
 +
...
 +
#define ALPHA_ISA 21064
 +
...
 +
#define MY_ISA 6400
  
*'''''m5/src/python/objects/__init__.py''''': Add the base name of your python file into the 'file_bases' list.
+
...
  
 +
#if THE_ISA == ALPHA_ISA
 +
    #define TheISA AlphaISA
 +
#elif THE_ISA == SPARC_ISA
 +
    #define TheISA SparcISA
 +
...
 +
#elif THE_ISA == MY_ISA
 +
    #define TheISA MyISA
 +
#else
 +
    #error "THE_ISA not set"
 +
#endif
  
'''Now build your model:'''
 
<pre>
 
scons build/ALPHA_SE/m5.debug CPU_MODELS=MY_CPU
 
 
</pre>
 
</pre>
If you have dual-core CPU use this to speed-up the compilation:
+
 
 +
* m5/src/arch/myisa/SConsopts - Edit the file so that the SCons build system will recognize your ISA
 
<pre>
 
<pre>
scons -j2 build/ALPHA_SE/m5.debug CPU_MODELS=MY_CPU
+
Import('*')
 +
 
 +
all_isa_list.append('myisa')
 
</pre>
 
</pre>
  
 +
=== MyISA Decoding & Instruction Object Creation - src/arch/MyISA/isa/*  ===
 +
At this point, the next major component for defining your own ISA is setting up the MyISA decoder. Please refer to the [[ISA_description_system | ISA description page]] for detailed specifics of
 +
the instruction object decoding and construction process.
  
'''Create and edit configuration files for your model:'''
+
We'll go over the files you will be using for your MyISA description here:
*m5/configs/test/MyCPUConfig.py: Define a configuration class w/corresponding parameters for your model. Look to 'FullO3Config.py' in the same directory for an example of how to do this.
+
* isa/*
*m5/configs/test/test.py: Import your model's configuration at the top of the file (i.e. 'import MyCPUConfig') and add in a parser option for your CPU model (e.g. '--my_cpu').  
+
** operands.isa
 
+
** base.isa
 +
** decoder.isa
 +
** main.isa
 +
** includes.isa
 +
* isa/formats/*
 +
** formats.isa
 +
** basic.isa
 +
** int.isa
 +
** branch.isa 
 +
** control.isa 
 +
** fp.isa 
 +
** mem.isa 
 +
** noop.isa 
 +
** tlbop.isa 
 +
** trap.isa 
 +
** unimp.isa 
 +
** unknown.isa 
 +
** util.isa
  
'''Test your model:'''
+
=== Testing MyISA ===
 +
'''Test That your decoder builds:'''
 
<pre>
 
<pre>
build/ALPHA_SE/m5.debug configs/example/se.py --my_cpu --cmd=<bin_path>
+
scons build/MYISA_SE/arch/MyISA/atomic_simple_cpu_exec.cc CPU_MODELS=AtomicSimpleCPU
 
</pre>
 
</pre>

Latest revision as of 04:33, 20 January 2010

Overview

First, make sure you have basic understanding of how an ISA description generates instructions within the M5 framework. A good start is the The M5 ISA description language page.

For this example, we will be constructing an ISA called MyISA which will just be a renamed version of the MIPS ISA. We will go through the steps of creating the files and configuration opions for an M5 ISA description.

Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description will allow your MyISA architecture (analagous to ALPHA,MIPS,SPARC,etc.) to be plugged into System-Call Emulation (SE) and Full-System (FS) simulations of any M5 CPU Model.

Syscall Emulation (SE) MyISA

Creating the Files for MyISA

The correct place to insert your ISA files in M5 is in the src/arch directory. In this directory, create another directory called 'myisa' to keep your code. For this example, we will copy the relevant files needed from the M5 MIPS ISA description.

cd src/arch
mkdir myisa
cd myisa
cp -r ../mips/*.hh ./
cp -r ../mips/*.cc ./

The relevant files are as follows:

  • isa_traits.hh/cc - <explanation here>
  • regfile.hh/cc, regfile/* - <explanation here>
  • process.hh/cc - <explanation here>
  • linux/* - <explanation here>
  • isa/* - <explanation here>
  • faults.hh/cc - <explanation here>

You need to make sure that all instances of MipsISA needs to be replaced with MyISA in the files.

perl -pe s/Mips/My/g ????

Making M5 Recognize MyISA

  • m5/build_opts/MYISA_SE - Create this file that allows M5 to recognize MyISA as a Syscall Emulation build option. It's contents should contain:
TARGET_ISA = 'myisa'
FULL_SYSTEM = 0
  • m5/src/arch/isa_specific.hh - Edit this file by adding a constant for MyISA and then adding MyISA to the #define if/else structure.
...
#define ALPHA_ISA 21064
...
#define MY_ISA 6400

...

#if THE_ISA == ALPHA_ISA
    #define TheISA AlphaISA
#elif THE_ISA == SPARC_ISA
    #define TheISA SparcISA
...
#elif THE_ISA == MY_ISA
    #define TheISA MyISA
#else
    #error "THE_ISA not set"
#endif

  • m5/src/arch/myisa/SConsopts - Edit the file so that the SCons build system will recognize your ISA
Import('*')

all_isa_list.append('myisa')

MyISA Decoding & Instruction Object Creation - src/arch/MyISA/isa/*

At this point, the next major component for defining your own ISA is setting up the MyISA decoder. Please refer to the ISA description page for detailed specifics of the instruction object decoding and construction process.

We'll go over the files you will be using for your MyISA description here:

  • isa/*
    • operands.isa
    • base.isa
    • decoder.isa
    • main.isa
    • includes.isa
  • isa/formats/*
    • formats.isa
    • basic.isa
    • int.isa
    • branch.isa
    • control.isa
    • fp.isa
    • mem.isa
    • noop.isa
    • tlbop.isa
    • trap.isa
    • unimp.isa
    • unknown.isa
    • util.isa

Testing MyISA

Test That your decoder builds:

scons build/MYISA_SE/arch/MyISA/atomic_simple_cpu_exec.cc CPU_MODELS=AtomicSimpleCPU