Difference between revisions of "Defining ISAs (as of M5 2.0 beta 3)"
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First, make sure you have basic understanding of the ISA description objects within the M5 framework. A good start is the [[The M5 ISA description language]] page. | First, make sure you have basic understanding of the ISA description objects within the M5 framework. A good start is the [[The M5 ISA description language]] page. | ||
| − | Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description | + | Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description will allow your MyISA |
| + | architecture (analagous to ALPHA,MIPS,SPARC,etc.) to be plugged into System Call and Full-System simulations of any M5 CPU Model. | ||
== Making M5 Recognize MyISA == | == Making M5 Recognize MyISA == | ||
Revision as of 20:14, 22 May 2007
- NOTE: THIS PAGE IS UNDER CONSTRUCTION. HOPE TO FINISH SOON!!!
Contents
Overview
First, make sure you have basic understanding of the ISA description objects within the M5 framework. A good start is the The M5 ISA description language page.
Your new ISA description, MyISA, will need to generate correct instructions for the different CPU models. More specifically, your MyISA description will allow your MyISA architecture (analagous to ALPHA,MIPS,SPARC,etc.) to be plugged into System Call and Full-System simulations of any M5 CPU Model.
Making M5 Recognize MyISA
MyISA Architecture - src/arch/MyISA/isa_traits.hh
MyISA Formats & Templates - src/arch/MyISA/formats/*.isa
MyISA Decoder - src/arch/MyISA/decoder.isa
Now Test Your Decoder:
scons build/MYISA_SE/arch/MyISA/atomic_simple_cpu_exec.cc CPU_MODELS=AtomicSimpleCPU
