Difference between revisions of "CPU Models"

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* [[InOrder]] - Specific documentation on how all of the pipeline stages work, and how to modify and create new CPU models based on it.
 
* [[InOrder]] - Specific documentation on how all of the pipeline stages work, and how to modify and create new CPU models based on it.
 
** [[InOrder Pipeline Stages | Pipeline Stages]]  
 
** [[InOrder Pipeline Stages | Pipeline Stages]]  
** [[InOrder Resource-Request Model]]  
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** [[InOrder Resource-Request Model | Resource-Request Modeling]]  
** [[InOrder Resource Pool]]  
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** [[InOrder Resource Pool | Resource Pool]]  
** [[InOrder Pipeline Description]]   
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** [[InOrder Pipeline Description | Pipeline Description]]   
 
** [[InOrder ToDo List]]  
 
** [[InOrder ToDo List]]  
  

Revision as of 18:01, 12 January 2010

Supporting classes

  • StaticInst - Used to hold static information and methods about specific binary instructions, such as addq's or subq's.
  • DynInst - Used to hold dynamic information about instructions in the pipeline, such as the PC or predicted target.
  • ThreadState - Used to store thread information that is generic across CPU models.
  • SimpleThread - Used by simple CPU models to store architected state and provide the ThreadContext interface.

Interfaces

  • ThreadContext - The ThreadContext class. Used to provide an interface for objects outside of the CPU to access the specific thread state.
  • ExecContext - The ExecContext interface. An implicit interface that is used by the ISA in order to access the CPU's architected state.