Difference between revisions of "ARM Implementation"

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(Created page with "===Supported features and modes=== ===Thumb support=== ===Special PC management===")
 
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===Thumb support===
 
===Thumb support===
 
===Special PC management===
 
===Special PC management===
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===IT State===
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===Boot loader===
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A simple bootloader for ARM is in the source tree under <code>system/arm/simple_bootloader</code>. It is only needed for MP linux booting, but can be used for UP linux and probably shouldn't cause any issues with a bare metal. The initial conditions of the bootloader running are the same as those ffor Linux, <code> r0 = 0; r1 = machine number; r2 = atags ptr;</code> and some special registers for the boot loader to use <code>r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register</code>. The bootloader works by reading the MPIDR register to determine the CPU number. CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt. When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.

Revision as of 11:13, 7 April 2011

Supported features and modes

Thumb support

Special PC management

IT State

Boot loader

A simple bootloader for ARM is in the source tree under system/arm/simple_bootloader. It is only needed for MP linux booting, but can be used for UP linux and probably shouldn't cause any issues with a bare metal. The initial conditions of the bootloader running are the same as those ffor Linux, r0 = 0; r1 = machine number; r2 = atags ptr; and some special registers for the boot loader to use r3 = start address of kernel; r4 = address of GIC; r5 = adderss of flags register. The bootloader works by reading the MPIDR register to determine the CPU number. CPU0 jumps immediately to the kernel while CPUn enables their interrupt interface and and wait for an interrupt. When CPU0 generates an IPI, CPUn reads the flags register until it is non-zero and then jumps to that address.