Difference between revisions of "InOrder ToDo List"

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(ISA Support)
Line 35: Line 35:
 
*ALPHA - completed
 
*ALPHA - completed
 
*MIPS - completed
 
*MIPS - completed
 +
*ARM - not completed
 
*X86 - not completed
 
*X86 - not completed
 
*SPARC - not completed
 
*SPARC - not completed
 +
*POWER - not completed
  
 
==Full System Support ==
 
==Full System Support ==

Revision as of 17:17, 29 August 2010

Python Configurability

  • Resource Configuration - How can we specify what resources are instantiated via the Python config files?
    • ResourceType - Type of resource (Enum type)
      • ResourceParams - Parameters for this type of resource
      • Request - List of requests for this type of resource (Enum type)
        • Latency - operation latency and issue latency (intra/inter thread)
      • Count - Number of such resource type
  • Pipeline Description
    • InstSchedule - Instruction schedule specified as a vector of InstClassSchedule
      • InstClassSchedule - Vector of schedules per instruction class - load/store, Int execute, FP execute, specialized inst, etc. (do we still want a distinction between front end and back end schedules?)
    • ResourceRequestList - Vector of ResourceRequest (per stage?)
      • ResourceRequest - Vector of requests for resources
    • ResourceType/Request options
  • Multithreading Models?
    • None (single threaded)
    • Fine-grained (switch context every cycle or every few cycles, like Ultrasparc T2)
    • Coarse-grained (switch context on thread stalls, like 'SwitchOnCacheMiss' currently)
    • SMT (all contexts active, like 'SMT' currently)

Simulation Speed

  • Instruction Schedule Work
    • Use Vector of Vectors instead of Priority Queue
    • Identify Instruction Schedule Types (via Tuple)
    • Cache Instruction Schedule, Generate On-Demand
    • Instructions walk through schedule by incrementing pointer instead of popping from queue
      • If dynamic schedule is needed, then copy the remaining part of schedule and let the instruction add/remove as it pleases
      • Can we cache dynamic schedules? Is there a better solution here?
  • Event-Sleeping Work
    • Sleep instructions waiting for an long-delay event
    • Sleep CPU w/no activity (partially implemented)

ISA Support

  • ALPHA - completed
  • MIPS - completed
  • ARM - not completed
  • X86 - not completed
  • SPARC - not completed
  • POWER - not completed

Full System Support

  • TBD

Checkpointing

  • TBD

Regression Tests

TBD

*Move some of these to Flyspray?*