Difference between revisions of "ISCA 2006 tutorial"
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==Introduction== | ==Introduction== | ||
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This half-day tutorial will introduce participants to the [[Main Page| M5 simulator system]]. M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.<P> | This half-day tutorial will introduce participants to the [[Main Page| M5 simulator system]]. M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.<P> | ||
We will be releasing version 2.0 of M5 in conjunction with this tutorial. Features new in 2.0 include: | We will be releasing version 2.0 of M5 in conjunction with this tutorial. Features new in 2.0 include: | ||
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* Ali G. Saidi is a Ph.D. candidate in the EECS Department at the University of Michigan, and wrote much of the platform code for Linux full-system simulation. He received a BS in electrical engineering from the University of Texas at Austin. | * Ali G. Saidi is a Ph.D. candidate in the EECS Department at the University of Michigan, and wrote much of the platform code for Linux full-system simulation. He received a BS in electrical engineering from the University of Texas at Austin. | ||
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Revision as of 17:18, 7 June 2006
Introduction
This half-day tutorial will introduce participants to the M5 simulator system. M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.We will be releasing version 2.0 of M5 in conjunction with this tutorial. Features new in 2.0 include:
- Multiple ISA support (Alpha, MIPS, and SPARC)
- An all-new, execute-in-execute out-of-order SMT CPU timing model, with no SimpleScalar license encumbrance
- All-new, message-oriented interface for memory system objects, designed to simplify the development of non-bus interconnects
- More extensive Python integration and scripting support
- Full-system simulation using unmodified Linux 2.4/2.6, HP Tru64 5.1, or L4Ka::Pistachio) (Alpha only at this time... coming in the future for MIPS and SPARC)
- Detailed timing of I/O device accesses and DMA operations
- Accurate, deterministic simulation of multiple networked systems
- Flexible, script-driven configuration to simplify specification of complex multi-system configurations
- Included network workloads such as Apache, NAT, and NFS
- Support for storing results from multiple simulations in a unified database (e.g. MySQL) for automated reporting and graph generation
Intended Audience
Researchers in academia or industry looking for a free, open-source, full-system simulation environment for processor, system, or platform architecture studies. Please register via the ISCA 2006 web page.
Tentative Outline
- M5 structure
- Object structure
- Intro to SimObjects
- Object builder
- Configuration language
- Specialization using C++ templates
- Object serialization (checkpointing)
- Events
- Object structure
- CPU models
- Simple functional model
- Detailed out-of-order model
- Sampling and warm-up support
- Memory & I/O system overview
- Cache models
- Interconnect models (busses, point-to-point networks)
- Coherence support
- I/O modeling
- Programmed I/O (uncached accesses)
- DMA I/O
- Ethernet model
- NIC device models
- Linux driver
- Link layer model
- Full-system modeling
- Building disk images
- Console and PAL code
- Running benchmarks via system init scripts
- Target kernel introspection support
- Statistics
- Built-in statistics types
- Adding new statistics
- Using the database back end
- Setting up a results database
- Using scripts to generate reports and graphs from the database
- Debugging techniques
- Built-in debugging support
- Tracing
- Runtime checking
- Gdb hooks
- Debugging target code (including kernels) using remote gdb
- Built-in debugging support
- ISA description language
- Adding your own instructions to the ISA
- Adding support for new ISAs
Speakers
- Steven K. Reinhardt is an associate professor in the EECS Department at the University of Michigan, and a principal developer of M5. He received a BS from Case Western Reserve University and an MS from Stanford University, both in electrical engineering, and a PhD in computer science from the University of Wisconsin-Madison. While at Wisconsin, he was the principal developer of the Wisconsin Wind Tunnel parallel architecture simulator.
- Ronald G. Dreslinski is a Ph.D. student in the EECS Department at the University of Michigan, and a developer of M5's memory system. He received a BSE in electrical engineering, a BSE in computer engineering, and a MSE in computer science and engineering all from the University of Michigan.
- Lisa R. Hsu is a Ph.D. candidate in the EECS Department at the University of Michigan, and was the developer of M5's Ethernet network interface model. She received a BSE in electrical engineering from Princeton University and an MSE in computer science and engineering from the University of Michigan.
- Kevin T. Lim is a Ph.D. student in the EECS Department at the University of Michigan, and the developer of M5's detailed CPU model. He received a BSE in computer engineering from the University of Michigan.
- Ali G. Saidi is a Ph.D. candidate in the EECS Department at the University of Michigan, and wrote much of the platform code for Linux full-system simulation. He received a BS in electrical engineering from the University of Texas at Austin.
