Difference between revisions of "X86 microop ISA"
| Line 470: | Line 470: | ||
=== Flags === | === Flags === | ||
| − | This microop does not set any flags. It is | + | This microop does not set any flags. It is optionally predicated. |
== Sext == | == Sext == | ||
| Line 531: | Line 531: | ||
== Ruflags == | == Ruflags == | ||
| + | === ruflags: Dest = user flags === | ||
| + | Store the user level flags into the Dest register. | ||
| + | |||
| + | === Flags === | ||
| + | This microop does not set any flags. | ||
== Wruflags == | == Wruflags == | ||
| + | === wruflags: user flags = Src1 ^ Src2 === | ||
| + | Set the user level flags to the exclusive or of the Src1 and Src2 registers. | ||
| + | |||
| + | === wruflagsi: user flags = Src1 ^ Imm === | ||
| + | Set the user level flags to the exclusive or of the Src1 register and the immediate Imm. | ||
| + | |||
| + | === Flags === | ||
| + | See above. | ||
== Br == | == Br == | ||
| + | === br: micropc = Src1 + Src2 === | ||
| + | Set the micropc to the sum of the Src1 and Src2 registers. This is a microcode branch. | ||
| + | |||
| + | === bri: micropc = Src1 + Imm === | ||
| + | Set the micropc to the sum of the Src1 register and immediate Imm. This is a microcode branch. | ||
| + | |||
| + | === Flags === | ||
| + | This microop does not set any flags. It is optionally predicated. | ||
== Rdip == | == Rdip == | ||
| + | === rdip: Dest = rIP === | ||
| + | Set the Dest register to the current value of rIP. | ||
| + | |||
| + | === Flags === | ||
| + | This microop does not set any flags. | ||
== Wrip == | == Wrip == | ||
| + | === wrip: rIP = Src1 + Src2 === | ||
| + | Set the rIP to the sum of the Src1 and Src2 registers. This causes a macroop branch at the end of the current macroop. | ||
| + | |||
| + | === wripi: micropc = Src1 + Imm === | ||
| + | Set the rIP to the sum of the Src1 register and immediate Imm. This causes a macroop branch at the end of the current macroop. | ||
| + | |||
| + | === Flags === | ||
| + | This microop does not set any flags. It is optionally predicated. | ||
= Load/Store Ops = | = Load/Store Ops = | ||
= Load immediate Op = | = Load immediate Op = | ||
Revision as of 17:02, 27 September 2007
Contents
- 1 Register Ops
- 2 Load/Store Ops
- 3 Load immediate Op
Register Ops
Add
add: Dest = Src1 + Src2
Adds the contents of the Src1 and Src2 registers and puts the result in the Dest register.
addi: Dest = Src1 + Imm
Adds the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
| CF and ECF | The carry out of the most significant bit. |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | The carry from the 4th to 5th bit positions. |
| SF | The sign of the result. |
| OF | Whether there was an overflow. |
Adc
adc: Dest = Src1 + Src2 + CF
Adds the contents of the Src1 and Src2 registers and the carry flag and puts the result in the Dest register.
adci: Dest = Src1 + Imm + CF
Adds the contents of the Src1 register, the immediate Imm, and the carry flag and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
| CF and ECF | The carry out of the most significant bit. |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | The carry from the 4th to 5th bit positions. |
| SF | The sign of the result. |
| OF | Whether there was an overflow. |
Sub
sub: Dest = Src1 - Src2
Subtracts the contents of the Src2 register from the Src1 register and puts the result in the Dest register.
subi: Dest = Src1 - Imm
Subtracts the contents of the immediate Imm from the Src1 register and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
| CF and ECF | The barrow into of the most significant bit. |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | The barrow from the 5th to 4th bit positions. |
| SF | The sign of the result. |
| OF | Whether there was an overflow. |
Sbb
sbb: Dest = Src1 - Src2 - CF
Subtracts the contents of the Src2 register and the carry flag from the Src1 register and puts the result in the Dest register.
sbbi: Dest = Src1 - Imm - CF
Subtracts the immediate Imm and the carry flag from the Src1 register and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags.
| CF and ECF | The barrow into of the most significant bit. |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | The barrow from the 5th to 4th bit positions. |
| SF | The sign of the result. |
| OF | Whether there was an overflow. |
Mul1s
mul1s: ProdHi:ProdLo = Src1 * Src2
Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
mul1si: ProdHi:ProdLo = Src1 * Imm
Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
Flags
This microop does not set any flags.
Mul1u
mul1u: ProdHi:ProdLo = Src1 * Src2
Multiplies the unsigned contents of the Src1 and Src2 registers and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
mul1ui: ProdHi:ProdLo = Src1 * Imm
Multiplies the unsigned contents of the Src1 register and the immediate Imm and puts the high and low portions of the product into the internal registers ProdHi and ProdLo, respectively.
Flags
This microop does not set any flags.
Mulel
mulel: Dest = ProdLo
Moves the value of the internal ProdLo register into the Dest register.
Flags
This microop does not set any flags.
Muleh
muleh: Dest = ProdHi
Moves the value of the internal ProdHi register into the Dest register.
Flags
This microop optionally sets the CF, ECF, and OF flags.
| CF and ECF | Whether ProdHi is non-zero |
| OF | Whether ProdHi is non-zero. |
Div1
div1
Quotient * Src2 + Remainder = Src1 Divisor = Src2
Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the contents of SrcReg2 is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
div1i:
Quotient * Imm + Remainder = Src1 Divisor = Imm
Begins a division operation where the contents of SrcReg1 is the high part of the dividend and the immediate Imm is the divisor. The remainder from this partial division is put in the internal register Remainder. The quotient is put in the internal register Quotient. The divisor is put in the internal register Divisor.
Flags
This microop does not set any flags.
Div2
div2
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
Dest = Src2 - number of bits shifted in above
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The contents of the register Src2 denote the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.
div2i
Quotient * Divisor + Remainder = original Remainder with bits shifted in from Src1
Dest = Imm - number of bits shifted in above
Performs subsequent steps of division following a div1 instruction. The contents of the register Src1 is the low portion of the dividend. The immediate Imm denotes the number of bits in Src1 that have not yet been used before this step in the division. Dest is set to the number of bits in Src1 that have not been used after this step. The internal registers Quotient, Divisor, and Remainder are updated by this instruction.
If there are no remaining bits in Src1, this instruction does nothing except optionally compute flags.
Flags
This microop optionally sets the EZF flag.
| EZF | Whether there are any remaining bits in Src1 after this step. |
Divq
divq: Dest = Quotient
Moves the value of the internal Quotient register into the Dest register.
Flags
This microop does not set any flags.
Divr
divr: Dest = Remainder
Moves the value of the internal Remainder register into the Dest register.
Flags
This microop does not set any flags.
Or
or: Dest = Src1 | Src2
Computes the bitwise or of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
ori: Dest = Src1 | Imm
Computes the bitwise or of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
| CF and ECF | Cleared |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | Undefined |
| SF | The sign of the result. |
| OF | Cleared |
And
and: Dest = Src1 & Src2
Computes the bitwise and of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
andi: Dest = Src1 & Imm
Computes the bitwise and of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
| CF and ECF | Cleared |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | Undefined |
| SF | The sign of the result. |
| OF | Cleared |
Xor
xor: Dest = Src1 | Src2
Computes the bitwise xor of the contents of the Src1 and Src2 registers and puts the result in the Dest register.
xori: Dest = Src1 | Imm
Computes the bitwise xor of the contents of the Src1 register and the immediate Imm and puts the result in the Dest register.
Flags
This microop optionally sets the CF, ECF, ZF, EZF, PF, AF, SF, and OF flags. There is nothing that prevents computing a value for the AF flag, but it's value will be meaningless.
| CF and ECF | Cleared |
| ZF and EZF | Whether the result was zero. |
| PF | The parity of the result. |
| AF | Undefined |
| SF | The sign of the result. |
| OF | Cleared |
Sll
sll: Dest = Src1 << Src2
Shifts the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
slli: Dest = Src1 << Imm
Shifts the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
| CF and ECF | The last bit shifted out of the result. |
| OF | The exclusive or of the what this instruction would set the CF flag to (if requested) and the most significant bit of the result |
Srl
srl: Dest = Src1 >>(logical) Src2
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
srli: Dest = Src1 >>(logical) Src2
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in sign extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
| CF and ECF | The last bit shifted out of the result. |
| OF | The most significant bit of the original value to shift |
Sra
sra: Dest = Src1 >>(arithmetic) Src2
Shifts the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
srai: Dest = Src1 >>(arithmetic) Src2
Shifts the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. Bits which are shifted in zero extend the result. The shift amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the shift amount is zero, no flags are modified.
| CF and ECF | The last bit shifted out of the result. |
| OF | Cleared |
Ror
ror
Rotates the contents of the Src1 register to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
rori
Rotates the contents of the Src1 register to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
| CF and ECF | The most significant bit of the result. |
| OF | The exclusive or of the two most significant bits of the original value. |
Rcr
rcr
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
rcri
Rotates the contents of the Src1 register through the carry flag and to the right by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
| CF and ECF | The last bit shifted out of the result. |
| OF | The exclusive or of the CF flag before the rotate and the most significant bit of the original value. |
Rol
rol
Rotates the contents of the Src1 register to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
roli
Rotates the contents of the Src1 register to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
| CF and ECF | The least significant bit of the result. |
| OF | The exclusive or of the most and least significant bits of the result. |
Rcl
rcl
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the Src2 register and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
rcli
Rotates the contents of the Src1 register through the carry flag and to the left by the value in the immediate Imm and writes the result into the Dest register. The rotate amount is truncated to either 5 or 6 bits, depending on the operand size.
Flags
This microop optionally sets the CF, ECF, and OF flags. If the rotate amount is zero, no flags are modified.
| CF and ECF | The last bit rotated out of the result. |
| OF | The exclusive or of CF before the rotate and most significant bit of the result. |
Mov
mov: Dest = Src2
Move the contents of the Src2 register into the Dest register.
movi: Dest = Imm
Move the contents of the immediate Imm into the Dest register.
Flags
This microop does not set any flags. It is optionally predicated.
Sext
sext: Dest = sign_extend(Src1, Imm)
Sign extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
Flags
This microop does not set any flags.
Zext
zext: Dest = zero_extend(Src1, Imm)
Zero extend the value in the Src1 register starting at the bit position in the immediate Imm, and put the result in the Dest register.
Flags
This microop does not set any flags.
Ruflag
ruflag
Reads the user level flag stored in the bit position specified by the immediate Imm and stores it in the register Dest.
The mapping between values of Imm and user level flags is show in the following table.
| 0 | CF (carry flag) |
| 2 | PF (parity flag) |
| 3 | ECF (emulation carry flag) |
| 4 | AF (auxiliary carry flag) |
| 5 | EZF (emulation zero flag) |
| 6 | ZF (zero flag) |
| 7 | SF (sign flag) |
| 10 | DF (direction flag) |
| 11 | OF (overflow flag) |
Flags
The EZF flag is always set. In the future this may become optional.
| EZF | Set if the value of the flag read was zero. |
Ruflags
ruflags: Dest = user flags
Store the user level flags into the Dest register.
Flags
This microop does not set any flags.
Wruflags
wruflags: user flags = Src1 ^ Src2
Set the user level flags to the exclusive or of the Src1 and Src2 registers.
wruflagsi: user flags = Src1 ^ Imm
Set the user level flags to the exclusive or of the Src1 register and the immediate Imm.
Flags
See above.
Br
br: micropc = Src1 + Src2
Set the micropc to the sum of the Src1 and Src2 registers. This is a microcode branch.
bri: micropc = Src1 + Imm
Set the micropc to the sum of the Src1 register and immediate Imm. This is a microcode branch.
Flags
This microop does not set any flags. It is optionally predicated.
Rdip
rdip: Dest = rIP
Set the Dest register to the current value of rIP.
Flags
This microop does not set any flags.
Wrip
wrip: rIP = Src1 + Src2
Set the rIP to the sum of the Src1 and Src2 registers. This causes a macroop branch at the end of the current macroop.
wripi: micropc = Src1 + Imm
Set the rIP to the sum of the Src1 register and immediate Imm. This causes a macroop branch at the end of the current macroop.
Flags
This microop does not set any flags. It is optionally predicated.
