Difference between revisions of "Main Page"
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==The M5 Simulator System== | ==The M5 Simulator System== | ||
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===News=== | ===News=== | ||
| − | + | We will be holding a second M5 tutorial on Sunday June 18 in conjunction with [ISCA 33|http://www.ece.neu.edu/conf/isca2006]. See our [ISCA 2006 tutorial] page for more information. We are also planning to release version 2.0 in time for the tutorial. | |
===Key features=== | ===Key features=== | ||
| − | + | * Pervasive object orientation. Major simulation structures (CPUs, busses, caches, etc.) are represented as objects, both externally and internally. M5's configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. M5's internal object orientation (using C++) provides in addition to the usual software engineering advantages. | |
| − | + | * Multiple interchangeable CPU models. M5 currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an out-of-order SMT-capable CPU; and a random memory-system tester. The first two models are use a common high-level ISA description (though only the Alpha ISA is supported at this time). | |
| − | + | * Event-driven memory system. M5 features a detailed, event-driven memory system including non-blocking caches and split-transaction busses. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; M5 currently includes a simple snooping cache coherence protocol. | |
| − | + | * Full-system capability. M5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability. | |
| − | + | * Multiprocessor / multi-system capability. Thanks to M5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping bus-based coherence protocol supported by the caches, M5 can model symmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks. | |
===Additional details=== | ===Additional details=== | ||
| − | + | * Application-only support. In application-only (non-full-system) mode, M5 can execute Alpha Linux or Tru64 binaries with OS emulation or SimpleScalar EIO trace files. | |
| − | + | * Platforms. M5 runs on Intel x86-compatible systems running Linux, OpenBSD, or Cygwin, and should be readily portable to other little-endian hosts and other Unix-like operating systems. Alpha binaries to run on M5 (including the full Linux kernel) can be built on x86 systems using gcc-based cross-compilation tools, so no Alpha hardware is needed to make full use of M5. | |
| − | + | * Provenance. Portions of M5 (EIO trace support and parts of our old detailed CPU model) were derived from SimpleScalar. These portions are being released under the SimpleScalar license. We have a new detailed CPU model that will eliminate this dependency, though this new model currently does not support full-system simulation or SMT. We are also grateful to the SimOS and SimOS/Alpha developers, as SimOS/Alpha was an invaluable reference platform during our development of full-system mode. | |
| − | + | * Licensing. M5 is being released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of M5 derived from other sources are also subject to the licensing restrictions of the original sources (notably SimpleScalar). | |
=== Download === | === Download === | ||
| − | The current public release of M5 is available at SourceForge. Please use the SourceForge tools to file bug reports, support/feature requests, and patches. We also ask that you use the m5sim-users mailing list hosted at SourceForge to ask questions regarding M5. You may also want to subscribe to the SourceForge m5sim-announcement list. | + | The current public release of M5 is available at [http://sourceforge.net/projects/m5sim SourceForge]. Please use the SourceForge tools to file bug reports, support/feature requests, and patches. We also ask that you use the [http://lists.sourceforge.net/lists/listinfo/m5sim-users m5sim-users] mailing list hosted at SourceForge to ask questions regarding M5. You may also want to subscribe to the SourceForge [http://lists.sourceforge.net/lists/listinfo/m5sim-announcement m5sim-announcement] list. |
===Documentation=== | ===Documentation=== | ||
Revision as of 14:49, 7 June 2006
Contents
The M5 Simulator System
M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.
News
We will be holding a second M5 tutorial on Sunday June 18 in conjunction with [ISCA 33|http://www.ece.neu.edu/conf/isca2006]. See our [ISCA 2006 tutorial] page for more information. We are also planning to release version 2.0 in time for the tutorial.
Key features
- Pervasive object orientation. Major simulation structures (CPUs, busses, caches, etc.) are represented as objects, both externally and internally. M5's configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. M5's internal object orientation (using C++) provides in addition to the usual software engineering advantages.
- Multiple interchangeable CPU models. M5 currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an out-of-order SMT-capable CPU; and a random memory-system tester. The first two models are use a common high-level ISA description (though only the Alpha ISA is supported at this time).
- Event-driven memory system. M5 features a detailed, event-driven memory system including non-blocking caches and split-transaction busses. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; M5 currently includes a simple snooping cache coherence protocol.
- Full-system capability. M5 models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
- Multiprocessor / multi-system capability. Thanks to M5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping bus-based coherence protocol supported by the caches, M5 can model symmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
Additional details
- Application-only support. In application-only (non-full-system) mode, M5 can execute Alpha Linux or Tru64 binaries with OS emulation or SimpleScalar EIO trace files.
- Platforms. M5 runs on Intel x86-compatible systems running Linux, OpenBSD, or Cygwin, and should be readily portable to other little-endian hosts and other Unix-like operating systems. Alpha binaries to run on M5 (including the full Linux kernel) can be built on x86 systems using gcc-based cross-compilation tools, so no Alpha hardware is needed to make full use of M5.
- Provenance. Portions of M5 (EIO trace support and parts of our old detailed CPU model) were derived from SimpleScalar. These portions are being released under the SimpleScalar license. We have a new detailed CPU model that will eliminate this dependency, though this new model currently does not support full-system simulation or SMT. We are also grateful to the SimOS and SimOS/Alpha developers, as SimOS/Alpha was an invaluable reference platform during our development of full-system mode.
- Licensing. M5 is being released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of M5 derived from other sources are also subject to the licensing restrictions of the original sources (notably SimpleScalar).
Download
The current public release of M5 is available at SourceForge. Please use the SourceForge tools to file bug reports, support/feature requests, and patches. We also ask that you use the m5sim-users mailing list hosted at SourceForge to ask questions regarding M5. You may also want to subscribe to the SourceForge m5sim-announcement list.
Documentation
- Overview and specific documentation about M5 is available on the Documentation page. Additionally, the M5 code is commented with doxgyen[1] comments. You can browse the documentation here.
- A list of Frequently Asked Questions is also avaible.
- The slides from our ISCA-32 tutorial held on June 5, 2005 in Madison, Wisconsin are also available. You may download them in Powerpoint (757KB), zipped Powerpoint (191KB), or two-per-page handouts in PDF (881KB). You may prefer the Powerpoint version so that you can watch the animated walk-through of the memory system call path.
- A more detailed (though increasingly dated) discussion of M5 can be found in our paper "Network-Oriented Full-System Simulation using M5" from the 2003 CAECW Workshop. If you use M5 in your research, we would apreciate a citation to this paper in any publications you produce.
A list of publications using the M5 simulator is also available. Please append to the list if you publish a paper using M5.
Acknowledgments
The M5 simulator is being developed with generous support from several sources, including the National Science Foundation, Hewlett-Packard, Intel, and IBM. Individuals working on M5 have also been supported by an Intel Fellowship (Nate Binkert), a Lucent Fellowship (Lisa Hsu), and a Sloan Research Fellowship (Steve Reinhardt).
This material is based upon work supported by the National Science Foundation under Grant Nos. CCR-0105503 and CCR-0219640. Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).
